In a semiconductor memory module, for example an FBDIMM (fully buffered dual in-line memory module), as set forth in FIG. 1A, semiconductor memory components B are arranged on both sides on a circuit board MP. The semiconductor memory components are driven by a control component SB. The control component and also the semiconductor memory components have a ball grid array housing BGA.
FIG. 1B shows a first surface, for example the top side of an FBDIMM. The control component, which contains a hub chip HC that drives the semiconductor memory components, is arranged in the center of the circuit board MP. The semiconductor memory components are situated on the left-hand and right-hand sides of the hub chip on the circuit board in two rows arranged parallel to one another.
FIG. 1C shows a second surface, for example the underside BOT of the FBDIMM of FIG. 1A. Here, too, the semiconductor memory components are arranged in two rows. Four memory chips ECC equipped with an error correction circuit for correcting memory errors are situated in the center of the underside of the circuit board MP. As on the top side as well, in each case four semiconductor memory components in two rows are arranged on the left-hand and right-hand sides of the four ECC memory chips.
In the case of the planar FBDIMM design illustrated in FIGS. 1A and 1B, precisely one memory chip is situated in each of the semiconductor memory components. The memory chips may contain DRAM (dynamic random access memory) memory cells, by way of example.
FIG. 2 shows a simplified illustration of a detail from a memory cell array SZF that is present on each of the memory chips SP. Within the memory cell array SZF, DRAM memory cells SZ are arranged in matrix-like fashion along word lines WL and bit lines BL. A DRAM memory cell comprises a selection transistor AT and a storage capacitor SC. In order to read out an item of information from the memory cell or in order to write an item of information to the memory cell, the selection transistor AT is switched into the on state by a corresponding control signal on the word line WL. The storage capacitor SC is connected to the bit line BL in low-resistance fashion. Consequently, via the bit line BL, the charge state of the storage capacitor can be read out in the case of a read access or a charge state can be stored in the storage capacitor in the case of a write access.
In order to carry out read and write accesses to the memory cells of the memory chip, the hub chip HC is driven by a memory controller. The control signals of the memory controller are fed to the FBDIMM memory module via a first and second bus. For this purpose, the first bus is connected to input and output contact terminals E1 and A1 on the top side TOP of the circuit board MP. The second bus is connected to input and output contact terminals E2 and A2 on the underside BOT of the circuit board MP. Each of the two buses can transmit control signals to the hub chip and also receive them from the hub chip.
If, in contrast to the planar FBDIMM design illustrated in FIGS. 1A and 1B, a so-called “stacked” FBDIMM memory module design is used, then in each case two memory chips (dual stacked) or four memory chips (quad stacked) are arranged in stacked fashion within the semiconductor memory components. In this embodiment, only one respective row having semiconductor components is situated on the top side and the underside of the semiconductor memory module. In the case of such a “stacked” memory module design, in accordance with a standardization, the signals fed to the input contact terminals E1 are fed to the hub chip HC via conductor tracks running on the surface TOP of the circuit board MP. Correspondingly, the signals fed from the hub chip to the output terminals A1 on the top side TOP are also fed via conductor tracks running on the top side of the circuit board MP.
By contrast, the input signals which are fed to the input contact terminals E2 on the underside BOT of the circuit board are fed via short conductor tracks on the underside of the circuit board to a contact hole (plated through hole) running through the circuit board. Via the plated through hole, the input contact terminals E2 are connected to conductor tracks running on an inner layer of the multilayer circuit board MP. The conductor tracks are led through a further plated through hole in the region of the hub chip to the top side TOP of the circuit board, from where they are led to the hub chip via a short conductor segment on the top side of the circuit board.
The signals which are fed from the hub chip to the output terminals A2 on the underside BOT of the circuit board are likewise fed to a further plated through hole via a short conductor segment on the top side of the circuit board. They are passed through the further plated through hole as far as an inner layer of the circuit board and then run via a conductor track on the inner layer of the circuit board as far as a further plated through hole, through which they emerge again on the underside BOT of the circuit board, from where they are fed to the output contact terminals A2 via a short conductor segment on the underside of the circuit board.
Such feeding of signals from the memory controller to the hub chip and from the hub chip to the memory controller is not possible, however, in the case of an FBDIMM in the planar design. FIG. 3 shows a detail from the top side TOP of the FBDIMM of FIG. 1B. The illustration shows the hub chip HC and the memory chips SP arranged in two rows on the left-hand side of the hub chip. Furthermore, arranged at the edge of the memory card are the input contact terminals E1 and the output contact terminals A1, to which the first bus is connected, which connects the FBDIMM memory module to the memory controller.
On account of the small space available, only some of the conductor tracks RXL1 leading from the input contact terminals E1 to the hub chip HC and only some of the conductor tracks TXL1 leading back from the hub chip HC to the output contact terminals A1 can run on the top side TOP of the circuit board. The remaining input and output contact terminals are led to the hub chip, and are led from the hub chip again to the output contact terminals, via conductor tracks running on inner layers of the multilayer circuit board MP. For this purpose, the input and output contact terminals are connected via short conductor segments to plated through holes extending from the top side TOP as far as the underside BOT of the circuit board. Via these plated through holes, the input and output contact terminals are connected to the conductor tracks internally in the circuit board. Situated in the region of the hub chip are further plated through holes, through which the conductor tracks are led from the inner layers to the surface TOP again, from where they are led directly to the hub chip.
FIG. 4 shows a cross section through the multilevel circuit board (multilayer circuit board) MP. The circuit board has a top side TOP and an underside BOT, between which a plurality of inner layers are arranged one above another. A layer L1 and L2 belong to a group G1 of layers which are arranged close to the top side TOP of the circuit board. A layer Ln−1 and Ln belong to a group G2 of layers which are arranged close to an underside BOT of the circuit board.
The circuit board MP has two continuous contact-making holes V1a and V1b in the region of an input contact terminal E1 and an output contact terminal A1 on the top side TOP of the circuit board, the contact-making holes extending from the top side TOP of the circuit board to the underside BOT of the circuit board. Two further continuous contact-making holes V2a and V2b are arranged in the region of an input contact terminal E2 and an output contact terminal A2 on the underside of the circuit board, the contact-making holes likewise extending from the top side TOP to the underside BOT of the circuit board. Alongside the continuous contact-making holes in the region of the input and output contact terminals, two further continuous contact-making holes V5a and V5b also exist, which likewise extend from the top side TOP to the underside BOT of the circuit board. The hub chip HC is arranged in the region of these two continuous contact-making holes.
An input signal RX1 fed from the memory controller via the first bus is applied to the input contact terminal E1 on the top side TOP of the circuit board. The input signal RX1 is fed via a conductor track RXL1 to an input terminal HCE1 of the hub chip HC. The conductor track RXL1 runs from the input contact terminal E1 via a short conductor segment on the top side of the circuit board as far as the continuous contact-making hole V1a and then runs within the continuous contact-making hole V1a as far as the layer L1. The conductor track RXL1 is then led along the layer L1 and led to the continuous contact-making hole V5a through which it passes to the top side TOP of the circuit board to the input terminal HCE1 of the hub chip. A conductor track RXL2, which connects the input contact terminal E2 on the underside of the circuit board to the input terminal HCE2 of the hub chip, likewise runs in the region of the layer L1. An input signal RX2, which is fed to the input contact terminal E2 from the memory controller via the second bus, is present at the input contact terminal E2 on the underside BOT of the circuit board. Consequently, only lines carrying input signals RX1 and RX2 that pass from the memory controller to the hub chip run on the layer plane L1.
At an output terminal HCA1, the hub chip generates an output signal TX1, which is fed via a conductor track TXL1 to the output contact terminal A1 on the top side TOP of the circuit board. The conductor track TXL1 runs through the continuous contact-making hole V5b as far as the layer plane Ln, on which the conductor track TXL1 is led as far as the continuous contact-making hole V1b. The conductor track TXL1 is led through the continuous contact-making hole V1b to the top side TOP of the circuit board again, and is led from there to the output contact terminal A1. The output contact terminal A1 is connected to the first bus, via which the output signal TX1 is fed to the memory controller. The first bus is thus formed as a bidirectional bus.
A further output terminal HCA2 of the hub chip is connected via a conductor track TXL2 to the output contact terminal A2 on the underside BOT of the circuit board. The conductor track TXL2 is led from the output terminal HCA2 of the hub chip through the continuous contact-making hole V5b likewise as far as the layer plane Ln, along which the conductor track TXL2 is led further as far as the continuous contact-making hole V2b. The conductor track TXL2 is led through the continuous contact-making hole V2b to the underside BOT of the circuit board. The output signal TX2 passes via a short conductor segment to the output contact terminal A2, which is connected to the second bus for transmitting the output signal TX2 from the hub chip to the memory controller. The output signals TX1 and TX2 from the hub chip to the memory controller thus run via conductor tracks on the inner layer Ln of the circuit board. The second bus is formed as a bidirectional bus since it transmits both input signals RX2 and output signals TX2 between the hub chip and the memory controller.
A “routing” of conductor tracks as shown in FIG. 4 results in a high degree of signal crosstalk, however, which is additionally intensified by using continuous contact-making holes, which represent a high inductance. However, the essential cause of the crosstalk is due to the fact that the signals which are sent from the memory controller to the hub chip are transmitted via conductor tracks in a layer plane that is arranged close to the top side TOP of the circuit board, and all the signals which are sent from the hub chip to the memory controller run on conductor tracks in a layer plane that is arranged close to the underside BOT of the circuit board. In particular, one problem is that the input signal RX2, when passing through the contact-making hole V2a, has to cross a plurality of reference planes internally within the circuit board before it passes from the underside BOT to the layer plane L1. Likewise, the output signal TX1 has to cross a plurality of reference planes internally within the circuit board via the continuous contact-making hole V5b before it reaches the layer plane Ln.